This application is based upon and claims priority from prior French Patent Application No. 00 12826, filed on Oct. 6, 2000, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to an asynchronous circuit with a micro-pipeline type execution structure for detecting and correcting soft error in digital integrated circuits. It also relates to an implementation method.
2. Description of the Prior Art
In integrated logic circuits a soft error is a non-recurring event that disturbs the signal at a particular time. This type of disturbance, which is of extremely short duration, causes unwanted changes in the signal emitted by one or more logic gates of the digital integrated circuit. Such disturbances are caused particularly by alpha particles radiation. A logic circuit affected by alpha particles undergoes a sudden change in the logic status of its output terminal. Soft error can be also caused by events such as electromagnetic phenomena, etc.
It has hitherto been known in the art to detect and treat soft error on the output of a logic calculation unit of synchronous circuits in which the operation is governed by the appearance of a particular event such as a clock signal. A variety of methods have been used to ensure that the signal output by a logic calculation unit is not affected by soft error.
One of these methods consists in using a majority logic circuit in which the input terminals are connected to the output terminal of the logic calculation unit via a sampling circuit. The output signal of the logic calculation unit is sampled at three different times: t, t+d and t+2d. The time needed to perform the three samplings must be greater than at least twice the maximum duration of a potential soft error in order to be sure of producing a correct output signal. The three sampled signals are applied to the input terminals of the majority logic circuit. This majority logic circuit selects the logic signal with the greatest probability of being correct when one of the sampled signals provides a signal that is different from the two others and can thereby be used to check the operation of the logic calculation unit.
If the three input terminals of the majority logic circuit have the same status it is highly unlikely that the logic calculation unit has committed an error during the time taken to effect the three samples. The output of the majority logic circuit thus has the same status as that of the three inputs and thus transmits the logic signal supplied by the logic calculation unit.
If, on the other hand, any two of the inputs of the majority logic circuit have the same logic status and the third input has a different logic status, it is unlikely that the logic calculation unit has committed the same error twice during the time taken to effect the three samples and that it has functioned correctly for the sampled output applied to the third input of the majority logic circuit. The samples with the same logic status are thus in the majority and consequently the output of the majority logic circuit adopts the same logic status to transmit the signal.
This method, which combines a circuit that samples a signal output by a logic calculation unit with a majority logic circuit, uses a temporal redundancy to process the soft error in synchronous integrated circuits. This method is based on the fact that the duration of the soft error is known.
Other methods for processing soft error are used in synchronous circuits. One such method, rather than using a temporal redundancy, uses a total or partial hardware redundancy by adding another logic calculation unit in addition to that to be checked and compares their output signals.
Nevertheless, there are a certain number of drawbacks to these methods for checking soft error in synchronous circuits.
Firstly, methods which use a hardware redundancy involve increases in costs that are unacceptable when such products are intended for industry producing mass consumer electronics.
There are also drawbacks to methods for checking soft error based on temporal redundancy. On the one hand, they increase the time required to pass through the logic path by adding a duration greater than twice the duration of the soft error.
On the other, when the logic calculation unit is performing a large number of logic operations the duration of the soft error may not be easy to establish. An error that disturbs the signal output by the logic calculation unit with a maximum duration that is normally of the order of a few hundred picoseconds then propagates and its impact at the end of a long logic path may transform a pulse measuring one hundred picoseconds into a pulse measuring one nanosecond due to the different propagation times of the different electrical paths. Therefore when large logic calculation units are used, methods for correcting soft error in synchronous circuits based on the type of temporal redundancy described above are difficult to implement, particularly where sampling is concerned, because the duration of the soft error may be variable.
Lastly, it is not possible in synchronous circuits to recalculate the correct value output by the logic calculation unit on the fly. When an error is detected in the signal on output of a logic calculation unit the entire instruction must be performed, which wastes time.
Until now soft error was only detected and processed in synchronous circuits. Asynchronous circuits operating as micro-pipelines were not protected against soft error because such circuits are still very little used in integrated circuits. In pipeline-asynchronous operating modes the lack of a clock signal to time the performance of instructions, the performance of instructions is broken down more than in synchronous operating modes.
FIG. 1 shows a succession of logic stages E0, E1, E2 of a micro-pipeline type asynchronous circuit of the prior art. Each logic stage E0, E1, E2 has the same structure. Thus logic stages E0, E1, E2 each include a logic calculation unit respectively numbered 9, 1 and 5, storage means composed of a latch circuit respectively numbered 10, 2 and 6, a control unit respectively numbered 11, 3 and 7, and a delay line respectively numbered 12, 4 and 8. The description states that a logic stage of an asynchronous circuit of the prior art will be considered with reference to FIG. 2.
The control unit 3 of logic stage E1 receives a signal Aout sent by control unit 7 of the next logic stage E2, together with a signal Rin sent by control unit 11 of the previous stage E0, both received via delay line 12. Control unit 3 of logic stage E1 is also provided to transmit a signal Rout to control unit 7 of the next logic stage E2, together with a signal Ain to control unit 11 of the previous stage E0.
Logic stages E0, E1 and E2 communicate using a local check. The operation of asynchronous circuits is based on the propagation of data and the use of a communication protocol that is used with request and acknowledgement signals. Thus logic stages E0, E1 and E2, and more particularly their respective control units 11, 3 and 7, interact by means of signals Rin and Rout, known as request signals, and signals Ain and Aout, known as acknowledgement signals.
FIG. 2 shows a standard micro-pipeline type asynchronous architecture of the prior art and particularly shows the logic stage El of FIG. 1. The same references are used for components already described with reference to FIG. 1.
Logic calculation unit 1 supplies an output signal Din that is applied to the input terminal of the storage means consisting of latch circuit 2. Latch circuit 2 transmits an output signal Dout that is applied to the logic calculation unit 5 of the next logic stage E2. Latch circuit 2 is controlled by control unit 3 using a data capture signal Lt. Control unit 3 receives the signals Rin and Aout and transmits signals Rout and Ain. Signal Rout is applied to a delay line 4 that delays transmission of signal Rout.
Signal Rin is a request signal transmitted to control unit 3 to trigger capture of the data output by logic calculation unit 1. Data capture begins as soon as signal Aout is received by control unit 3 indicating that the calculation performed by the next logic stage E2 is complete, i.e., that the next stage E2 is ready to receive data. Reception by control unit 3 of signals Rin and Aout causes data capture signal Lt to be sent to latch circuit 2. This data capture signal Lt controls latch circuit 2 to record the state of signal Din at instant Lt. Latch circuit 2 may, for example, be a bistable circuit that temporarily stores binary data Din on output of logic circuit 1, thereby constituting a buffer memory. The request signal Rout is immediately sent by control unit 3 to the control unit of the next logic stage E2 to trigger capture of the data on output of logic calculation unit 5. On the output terminal of latch circuit 2 the signal Dout is transmitted to logic calculation unit 5. Latch circuit 2 is again set to store binary data Din. Launch of the operation to trigger capture of data on output of logic calculation unit 5 belonging to the next logic stage E2 by means of signal Rout may be delayed by means of delay line 4. Finally control unit 3 sends the previous logic stage an acknowledgement signal Ain signifying that logic stage E1 is ready to receive data.
However, this type of asynchronous circuit of the prior art is not designed to manage calculation errors caused by soft error.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.
A main aim of the present invention is to overcome malfunctions due to soft error in micro-pipeline type asynchronous logic circuits to provide asynchronous logic circuits that are protected against soft error.
Another aim of the invention is to implement a method for detecting and correcting soft error in asynchronous circuits designed to be applied to any micro-pipeline type asynchronous circuit in order to execute instructions.
The invention relates to an asynchronous circuit with a micro-pipeline type method of executing instructions suitable for detecting and correcting soft error in digital integrated circuits, comprising at least one logic stage, each logic stage comprising a logic calculation unit whose output terminal transmits an output signal, a first recording means one of the input terminals of which is connected to the output terminal of the logic calculation unit, a control unit one of whose three output terminals transmits a first data capture signal applied to the second input terminal of the first recording means, the other two output terminals of the control unit being respectively connected to an input terminal of the control unit of the previous logic stage, and to an input terminal of the control unit of the next logic stage by means of a delay line, wherein said asynchronous circuit also comprises a second recording means one of whose input terminals is connected to the output terminal of the logic calculation unit, means in the control unit for delaying the first data capture signal and providing a second data capture signal that is applied to the second recording means, a comparer circuit one of whose input terminals is connected to the output terminal of the first recording means and whose other input terminal is connected to the output terminal of the second recording means, said comparer circuit supplying an output signal that indicates in a first status that no soft error is present and in a second status that a soft error is present, and a programmable delay line whose first input terminal is connected to the output terminal of the comparer circuit, a second input terminal being connected to the output terminal of the delay line via a first delayed path and a last input terminal being connected to the output terminal of the delay line via a second non-delayed path.
The invention also relates to a method for detecting and correcting a soft error in micro-pipeline type asynchronous circuits consisting of at least one logic stage, wherein it can be applied to each logic stage and comprises the following stages:
a) recording in a first recording means the status of a signal output by a calculation unit;
b) recording in a second recording means the status of the said signal output by the said logic calculation unit with a delay longer than the pulse duration of a soft error;
c) comparing the recorded signals in a comparer circuit to transmit a signal carrying either information corresponding to a first status in which the compared signals are identical or information corresponding to a second status in which the compared signals are different, and
for the first status:
d1) providing a request signal for the control unit of the next logic stage without any delay,
or for the second status:
d2) recording the status of the signal output by the logic calculation unit a second time after another delay that is longer than the pulse duration of an error, and then sending a request signal to the control unit of the next logic stage with a delay twice as long as the pulse duration of a soft error.